The present invention relates generally to mechanisms for synchronizing data or signal transfer across clocked logic domains, and more particularly, to synchronizing multi-bit digital data or signal transfer between asynchronously clocked logic domains.
Within a single computing system, a number of different components or subsystems may operate at different frequencies. In particular, various components or subsystems utilized for the construction of a computing system may independently operate at different frequencies, such as in microprocessors and micro-controllers, where certain components or subsystems have a faster rate of operation than the operating frequencies of other system components or subsystems. Therefore, typically, it is desirable to devise computing systems with the ability to support multiple domains, which may operate at different frequencies.
For instance, most computing systems typically include a number of electronic circuits referred to as “clocked logic domains” that operate independently based on electrical “timing” or “clock” signals. Such clock signals are used to control and coordinate the activities of the computing system's various components or subsystems. One of the clock signals, the system clock signal, is a reference clock signal to which the various components or subsystems of the computer synchronize their operation. The computing system's components or subsystems generally include device clock synthesizer to generate a device clock signal synchronized to the system clock signal.
A particular device interface, or bus operating at a specific frequency, may define a distinct clocked logic domain. A variety of clocked systems may include one or more clock synthesizers, clock controllers or timers, such as a real time clock generator, an operating system timer, or an analog to digital converter controller that may require synchronizing transfer of multiple bits of data between asynchronous clock domains. However, synchronization of data transfer, particularly between various clocked logic domains presents a number of problems.
While transferring digital data or signals between multiple clocked logic domains in a clocked system, one problem involves synchronization, such as by using storage elements or other hardware so that the timing of the digital data or signals transmitted is properly aligned at the receiving end. In doing so, the data or signals being transferred from one clocked logic domain may be delayed by one or more clock cycles so that the data or signals may be synchronized with the clock signals in another clocked logic domain, as an example. However, providing such synchronization may cause undesirable and sometimes unpredictable delays in the communications path or the data path. This may result in significant performance degradation and/or lack of data or signal integrity.
Using a single bit synchronizer each bit of the multi-bit digital data or signal may be individually synchronized. However, there is a significantly high probability of transmission of an incorrect value across clock domains. Therefore, a clocked system may not be maintained fully synchronous because of the erroneous nature of the data transfer. In addition, a single bit synchronizers based scheme may impose restriction on updating the data in the source clock domain so that data is not corrupted during transfer.
Unfortunately, such single bit synchronization arrangement or mechanism may employ the same number of one-bit synchronizers as the number of bits in the multi-bit digital data or signal. For example, circuitry including at least 32 one-bit synchronizers may be generally required to send 32-bit data, consuming a significant amount of hardware and real estate. For situations where one clock may be removed on a temporary basis, maintaining adequate data or signal integrity while performing synchronization on a bit-by-bit basis, a synchronized data transfer may be even more difficult. Consequently, such an arrangement, or mechanism may be inadequate or inefficient for synchronizing multi-bit digital data or signal. Accordingly, these techniques may be unable to appropriately synchronize the transfer of multi-bit digital data or signal across multiple independently clocked logic domains while maintaining sufficient data or signal integrity. Thus, a technique is desired for transferring multi-bit digital data or signal between multiple clocked logic domains that reduces or addresses these problems.
Therefore, it is desirable to synchronously transfer multi-bit digital data or signal across multiple clocked domains.